| S No |
Year |
Project Title |
|---|
| 1 |
2022 |
Energy-Efficient Approximate Compressor Design for Error-Resilient Digital Signal Processing |
| 2 |
2022 |
Entropy encoder for low-power low-resources high-quality CFA image compression |
| 3 |
2022 |
Error-Correction Coding Using Polynomial Residue Number System |
| 4 |
2022 |
TECED: A Two-Dimensional Error-Correction Codes Based Energy-Efficiency SRAM Design |
| 5 |
2022 |
Design and implementation of error detection and correction system for semiconductor memory applications |
| 6 |
2022 |
CapCAM: A Multilevel Capacitive Content Addressable Memory for High-Accuracy and High-Scalability Search and Compute Applications |
| 7 |
2022 |
Error Correction Scheme with Decimal Matrix Code for SRAM Emulation TCAMs |
| 8 |
2022 |
A Ternary Based Soft Error Resilient SRAM Content Addressable Memory with Improved security using checksum method |
| 9 |
2022 |
A new method for designing an efficient switching median filter using VLSI architecture to remove salt and pepper noise |
| 10 |
2022 |
MEGA-MAC: A Merged Accumulation based Approximate MAC Unit for Error Resilient Applications |
| 11 |
2022 |
Design of 16-Bit Vedic Multiplier Using Modified Logic Gates and BEC Technique |
| 12 |
2022 |
Mobile Networks-on-Chip Mapping Algorithms for Optimization of Latency and Energy Consumption |
| 13 |
2022 |
A Dynamic Hybrid Decoder Apprroach Using EG-LDPC Codes for Signal Processing Applications |
| 14 |
2022 |
A New VLSI Architecture for High-Performance Parallel Turbo Decoder |
| 15 |
2022 |
Successive Cancellation Polar Decoder Implementation using Processing Elements |
| 16 |
2022 |
. Implementation of Low-Power BIST Using Bit Swapping Complete Feedback Shift Register (BSCFSR) |
| 17 |
2022 |
A Proposal for Design and Implementation of a Low Power Test Pattern Generator for BIST Applications |
| 18 |
2022 |
A contemporaneous input vector monitoring Bist architecture using memory |
| 19 |
2022 |
Design of efficient binary-coded decimal adder in QCA technology with a regular clocking scheme |
| 20 |
2022 |
An Efficient VLSI design of Median Filters using 8-bit Data Comparators in Image Applications |
| 21 |
2022 |
Low power low area VLSI implementation of adaptive FIR filter using DA for decision feedback equalizer |
| 22 |
2022 |
Novel VLSI Architecture for Fractional-Order Correntropy Adaptive Filtering Algorithm |
| 23 |
2022 |
VLSI Implementation of a Real-time Modified Decision-based Algorithm for Impulse Noise Removal |
| 24 |
2022 |
An Efficient Approximation Look Up Table Based Distributed Arithmetic (DA) VLSI Architecture for Finite Impulse Response |
| 25 |
2022 |
High-performance 3–2 Compressor Using Efficient XOR-XNOR in Nanotechnology |
| 26 |
2022 |
A Variant of Long Multiplication Design with Low Power and Area Using Modified 7: 3 Compressor for Biomedical Applications |
| 27 |
2022 |
Energy-Efficient Approximate Compressor Design for Error-Resilient Digital Signal Processing |
| 28 |
2022 |
Low power Dadda multiplier using approximate almost full adder and Majority logic based adder compressors |
| 29 |
2022 |
Low-Power Low-Area Near-Lossless Image Compressor for Wireless Capsule Endoscopy |
| 30 |
2021 |
Design and analysis of High speed wallace tree multiplier using parallel prefix adders for VLSI circuit designs |
| 31 |
2021 |
Implementation of optimized digital filter using sklansky adder and kogge stone adder |
| 32 |
2021 |
Analysis of 8-bit Vedic Multiplier using high speed CLA Adder |
| 33 |
2021 |
An Efficient Implementation of FIR Filter Using High Speed Adders For Signal Processing Applications |
| 34 |
2021 |
Design of 8 bit and 16 bit Reversible ALU for Low Power Applications |
| 35 |
2021 |
High speed and efficient ALU using modified booth multiplier |
| 36 |
2021 |
Design of Area Optimized Arithmetic and Logical Unit for Microcontroller |
| 37 |
2021 |
Modified High Speed 32-bit Vedic Multiplier Design and Implementation |
| 38 |
2021 |
Application of Vedic Multiplier: Design of a FIR Filter |
| 39 |
2021 |
Analysis of 32-Bit Multiply and Accumulate unit (MAC) using Vedic Multiplier |
| 40 |
2021 |
Design and Evaluation of a FIR Filter Using Hybrid Adders and Vedic Multipliers |
| 41 |
2021 |
High Performance, Low Power Architecture of 5-stage FIR Filter using Modified Montgomery Multiplier |
| 42 |
2021 |
Controller Architecture for Memory BIST Algorithms |
| 43 |
2021 |
Realization of Built-In Self-Test(BIST) Enabled Memory(RAM) Using Verilog and Implementation in Spartan6 FPGA board |
| 44 |
2021 |
A High-Performance Symmetric Hybrid Form Design for High-Order FIR Filter |
| 45 |
2021 |
FPGA Implementation of Symmetric Systolic FIR Filter using Multi-channel Technique |
| 46 |
2021 |
Power efficient FIR filter Architecture using Distributed Arithmetic Algorithm |
| 47 |
2021 |
Design of FIR filter based on FPGA |
| 48 |
2021 |
Power efficient FIR filter Architecture using Distributed Arithmetic Algorithm |
| 49 |
2021 |
Design and Analysis of LFSR based Random Number generator |
| 50 |
2021 |
VLSI implementation of Turbo coder for lte using Verilog |
| 51 |
2021 |
A Self-Timed Ring based TRNG with Feedback Structure for FPGA Implementation |
| 52 |
2021 |
Area Efficient and Low Power Multiplexer based Data Comparator for Median filter in Denoising Application |
| 53 |
2021 |
Low Power SEC-DED Hamming Code Using Reversible Logic |
| 54 |
2021 |
Design of Reversible Shift Registers Minimizing Number of Gates, Constant Inputs and Garbage Outputs |
| 55 |
2021 |
Design and performance analysis of Subtractor using 2:1 multiplexer using multiple logic families |
| 56 |
2021 |
Leakage Power Reduction in CMOS Logic Circuits Using Stack ONOFIC Technique adder |
| 57 |
2021 |
Power Efficient Design of Adiabatic Approach for Low Power VLSI Circuits |
| 58 |
2021 |
Power Efficient Design of Adiabatic Approach for Low Power VLSI Circuits |
| 59 |
2021 |
Review On LFSR For LOW Power BIST |
| 60 |
2021 |
Designing of Multiplexer and De-Multiplexer using different Adiabatic Logic |
| 61 |
2021 |
A Novel Area Efficient Parity Generator and Checker Circuits Design Using QCA |
| 62 |
2021 |
Design of Multiplexer Using Actin Quantum Cellular Automata |
| 63 |
2021 |
Design of a High-Performance 2-bit Magnitude Comparator Using Hybrid Logic Style |
| 64 |
2021 |
Design and Implementation of Primitive Cells, Full Adder, Full Subtractor, and Multiplier using Modified Gate Diffusion Input Logic |
| 65 |
2021 |
Realization of Power Efficient FIR Filters using Hybrid Accurate-Inaccurate Adder Architecture |
| 66 |
2021 |
Controller Architecture for Memory BIST Algorithms |
| 67 |
2021 |
Regeneration of Test Patterns for BIST by Using Artificial Neural Networks |
| 68 |
2021 |
Realization of Built-In Self Test(BIST) Enabled Memory(RAM) Using VHDL and Implementation in Spartan6 FPGA board |
| 69 |
2021 |
Test Scheduling for Low Transition Reusable LFSR based BIST in 3-D Stacked ICs |
| 70 |
2021 |
A Self-Timed Ring based TRNG with Feedback Structure for FPGA Implementation |
| 71 |
2021 |
Chaotic Ring Oscillator Based True Random Number Generator Implementations in FPGA |
| 72 |
2021 |
Chaotic True Random Number Generator for Secure Communication Applications |
| 73 |
2021 |
Design and Synthesis of LFSR based Random Number Generator |
| 74 |
2021 |
Design of LFSR Circuit based on High Performance XOR gate |
| 75 |
2021 |
A High-Performance Symmetric Hybrid Form Design for High-Order FIR Filters |
| 76 |
2021 |
FPGA Implementation of Symmetric Systolic FIR Filter using Multi-channel Technique |
| 77 |
2021 |
High Performance, Low Power Architecture of 5-stage FIR Filter using Modified Montgomery Multiplier |
| 78 |
2021 |
High Performance, Low Power Architecture of 5-stage FIR Filter using Modified Montgomery Multiplier |
| 79 |
2021 |
Power efficient FIR filter Architecture using Distributed Arithmetic Algorithm |
| 80 |
2021 |
Application of Vedic Multiplier: Design of a FIR Filter |
| 81 |
2021 |
Design of FIR filter based on FPGA |
| 82 |
2021 |
Realization of Power Efficient FIR Filters using Hybrid Accurate-Inaccurate Adder Architecture |
| 83 |
2019 |
Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications |
| 84 |
2019 |
Architecture Optimization and Performance Comparison of NonceMisuse-Resistant Authenticated Encryption Algorithms |
| 85 |
2019 |
TOSAM:AnEnergy-EfficientTruncation-andRoundingBasedScalableApproximate Multiplier |
| 86 |
2019 |
Design And Analysis Of Approximate Redundant Binary Multipliers |
| 87 |
2019 |
Rounding Technique Analysis Of Power-Area & Energy Efficient Approximate Multiplier Design |
| 88 |
2019 |
A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapath. |
| 89 |
2019 |
Low Power High Accuracy Approximate Multiplier Using Approximate High Order Compressors |
| 90 |
2019 |
Efficient Modular Adder Designs Based on Thermometer & One-Hot Encoding |
| 91 |
2019 |
Error Detection And Correction In SRAM Emulated TCAMs |
| 92 |
2019 |
Efficient Design For Fixed Width Adder Tree |
| 93 |
2019 |
Area –Time Efficient Streaming Architecture For Architecture For FAST And BRIEF Detector |
| 94 |
2019 |
Hard Ware Efficient Post Processing Architecture For True Random Number Generators |
| 95 |
2019 |
A Two Speed Radix -4 Serial –Parallel Multiplier |
| 96 |
2019 |
Low power approximate unsigned multipliers with configurable error recovery |
| 97 |
2019 |
Energy Quality Scalable Adders Based On Non Zeroing Bit Truncation |
| 98 |
2019 |
Double MAC On A DSP Boosting The Performance Of Convolutional Neural Networks On FPGAS |
| 99 |
2019 |
A Low-Power Parallel Architecture for Linear Feedback Shift Registers |
| 100 |
2019 |
Ultra-low-voltage GDI-based hybrid full adder design for area and energyefficient computing systems |
| 101 |
2019 |
Design Of Area Efficient And Low Power 4-Bit Multiplier Based On Fullswing GDI technique |
| 102 |
2019 |
Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications |
| 103 |
2019 |
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced DataIndependent Read Port Leakage for Array Augmentation in 32-nm CMOS |
| 104 |
2019 |
Column selection enabled 10 T SRAM utilizing shared diff VDD WRITE and dropped VDD read for FFT on real data |
| 105 |
2019 |
Cell-state-distribution –assisted threshold voltage detector for NAND flash memory |
| 106 |
2019 |
Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis in Domino Logic |
| 107 |
2019 |
An Approach to LUT Based Multiplier for Short Word Length DSP Systems |
| 108 |
2019 |
Novel High speed Vedic Multiplier proposal incorporating Adder based on Quaternary Signed Digit number system |
| 109 |
2019 |
FPGA Implementation of an Improved Watchdog Timer for Safety-critical Applications |
| 110 |
2019 |
Unbiased Rounding for HUB Floating-point Addition |
| 111 |
2019 |
A Low-Power Yet High-Speed Configurable Adder for Approximate Computing |
| 112 |
2019 |
A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design |
| 113 |
2019 |
The Design and Implementation of Multi – Precision Floating Point Arithmetic Unit Based on FPGA |
| 114 |
2019 |
Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction |
| 115 |
2019 |
Efficient Modular Adders based on Reversible Circuits |
| 116 |
2019 |
MAES: Modified Advanced Encryption Standard for Resource Constraint Environments |
| 117 |
2019 |
Chip Design for Turbo Encoder Module for In-Vehicle System |
| 118 |
2019 |
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates |
| 119 |
2018 |
First experimental demonstration of a scalable linear majority gate based on spin waves |
| 120 |
2018 |
Design of Majority Logic Based Comparator |
| 121 |
2018 |
Novel Cascadable Magnetic Majority Gates for Implementing Comprehensive Logic Functions |
| 122 |
2018 |
Comparator Design using CTL and Outputwired based Majority Gate |
| 123 |
2018 |
Design of Generalized Pipeline Cellular Array in Quantum-Dot Cellular Automata |
| 124 |
2018 |
Size Optimization of MIGs with an Application to QCA and STMG Technologies |
| 125 |
2018 |
Spin-based majority gates for logic applications |
| 126 |
2018 |
Finite Hyperplane Codes: Minimum Distance and Majority-Logic Decoding |
| 127 |
2018 |
Adapting Computer Arithmetic Structures to Sustainable Supercomputing in Low-Power, Majority-Logic Nanotechnologies |
| 128 |
2018 |
A Novel Design of Quantum-Dots Cellular Automata Comparator Using FiveInput Majority Gate |
| 129 |
2018 |
Modified majority logic decoding of Reed–Muller codes using factor graphs |
| 130 |
2018 |
Characteristics of signal propagation in multiferroic majority logic gates subjected to thermal noise |
| 131 |
2018 |
Bit error probability analysis for majority logic decoding of CSOC codes over fading channels |
| 132 |
2018 |
Majority Voting-Based Reduced Precision Redundancy Adders |
| 133 |
2018 |
On the Decoding Radius Realized by Low-Complexity Decoded Non-Binary Irregular LDPC Codes |
| 134 |
2018 |
Design of 2 s Complement of 4-Bit Binary Numbers Using Quantum Dot Cellular Automata |
| 135 |
2018 |
Majority Logic: Prime Implicants and n-Input Majority Term Equivalence |
| 136 |
2018 |
A Simple Synthesis Process for Combinational QCA Circuits: QSynthesizer |
| 137 |
2018 |
Test Pattern Generator for Majority Voter based QCA Combinational Circuits targeting MMC Defect |
| 138 |
2018 |
Two Bit Overlap: A Class of Double Error Correction One Step Majority Logic Decodable Codes |
| 139 |
2018 |
A Majority-Based Imprecise Multiplier for Ultra-Efficient Approximate Image Multiplication |
| 140 |
2018 |
Design and Analysis of Majority Logic Based Approximate Adders and Multipliers |
| 141 |
2018 |
A CMOS Majority Logic Gate and Its Application to One-Step ML Decodable Codes |
| 142 |
2018 |
Novel Reliable QCA Subtractor Designs using Clock zone based Crossover |
| 143 |
2018 |
Inversions Optimization in XOR-Majority Graphs with an Application to QCA |
| 144 |
2018 |
Exact Synthesis of Boolean Functions in Majority-of-Five Forms |
| 145 |
2018 |
New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata |
| 146 |
2018 |
A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes |
| 147 |
2018 |
Design and Simulation of 4-bit QCA BCD Full-adder |
| 148 |
2018 |
An Efficient Design of 4 - to - 2 Encoder and Priority Encoder Based on 3-dot QCA Architecture |
| 149 |
2018 |
An Effective Design of 2 : 1 Multiplexer and 1 : 2 Demultiplexer using 3-dot QCA Architecture |
| 150 |
2018 |
High Speed Memory Cell with Data Integrity in QCA |
| 151 |
2018 |
Design of an Efficient Multilayer Arithmetic Logic Unit in Quantum-Dot Cellular Automata (QCA) |
| 152 |
2018 |
Comparative Analysis of Full Adder Custom Design Circuit using Two Regular Structures in Quantum-Dot Cellular Automata (QCA) |
| 153 |
2018 |
Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis |
| 154 |
2018 |
QCA Realization of Reversible Gates Using Layered T Logic Reduction Technique |
| 155 |
2018 |
QCA Based Error Detection Circuit for Nano Communication Network |
| 156 |
2018 |
Hamming Code Generators using LTEx Module of Quantum-dot Cellular Automata |
| 157 |
2018 |
A Design and Implementation of Montgomery Modular Multiplier |
| 158 |
2018 |
Modified Binary Multiplier Circuit Based on Vedic Mathematics |
| 159 |
2018 |
Performance Analysis of Wallace Tree Multiplier with Kogge Stone Adder using 15-4 Compressor |
| 160 |
2018 |
Implementation of Floating Point Unit based on Booth Multiplier and Compressor Adder |
| 161 |
2018 |
Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm |
| 162 |
2018 |
Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over GF(2m) Based on Reordered Normal Basis |
| 163 |
2018 |
Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery |
| 164 |
2018 |
Energy-efficient VLSI implementation of multipliers with double LSB operands |
| 165 |
2018 |
Design and Analysis of Approximate Redundant Binary Multipliers |
| 166 |
2018 |
Low-Power High-Accuracy Approximate Multiplier Using Approximate HighOrder Compressors |
| 167 |
2018 |
TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier |
| 168 |
2018 |
Design Of Area Efficient And Low Power 4-Bit Multiplier Based On Full- swing GDI technique |
| 169 |
2018 |
Low Space Complexity GF(2m) Multiplier for Trinomials Using n -Term Karatsuba Algorithm |
| 170 |
2018 |
Rounding Technique Analysis for Power-Area & Energy Efficient Approximate Multiplier Design |
| 171 |
2018 |
Design and Analysis of High Performance Multiplier Circuit |
| 172 |
2018 |
Comparative Performance Analysis of Karatsuba Vedic Multiplier with Butterfly Unit |
| 173 |
2018 |
A Low Power Binary Square rooter using Reversible Logic |
| 174 |
2018 |
LDPC check node implementation using reversible logic |
| 175 |
2018 |
Area Efficient VLSI Architecture for Reversible Radix-2 FFT Algorithm using Folding Technique and Reversible Gate |
| 176 |
2018 |
Efficient designs of reversible latches with low quantum cost |
| 177 |
2018 |
Structured decomposition for reversible Boolean functions |
| 178 |
2018 |
Design and synthesis of improved reversible circuits using AIG- and MIG-based graph data structures |
| 179 |
2018 |
Design of Reversible Arithmetic Logic Unit with Built-In Testability |
| 180 |
2018 |
Embedding Functions Into Reversible Circuits: A Probabilistic Approach to the Number of Lines |
| 181 |
2018 |
Chaos-Based Bitwise Dynamical Pseudorandom Number Generator On FPGA |
| 182 |
2018 |
A High Performance Full-Word Barrett Multiplier Designed for FPGAs with DSP Resources |
| 183 |
2018 |
Design and Execution of Enhanced Carry Increment Adder using Han-Carlson and Kogge-Stone adder Technique : Han-Carlson and Kogge-Stone adder is used to increase speed of adder circuitry |
| 184 |
2018 |
Design and Performance Comparison among Various types of Adder Topologies |
| 185 |
2018 |
A New High-speed and Low area Efficient Pipelined 128-bit Adder Based on Modified Carry Look-ahead Merging with Han-Carlson Tree Method |
| 186 |
2018 |
16 Bit Power Efficient Carry Select Adder |
| 187 |
2018 |
Implementation of an XOR Based 16-bit Carry Select Adder for Area, Delay and Power Minimization |
| 188 |
2018 |
Carry based approximate full adder for low power approximate computing |
| 189 |
2018 |
Analysis of 1- bit full adder using different techniques in Cadence 45nm Technology |
| 190 |
2018 |
Area Efficient Architecture for high speed wide data adders in Xilinx FPGAs |
| 191 |
2018 |
Design of Delay Efficient Hybrid Adder for High Speed Applications |
| 192 |
2018 |
Power-Delay-Product, Area and Threshold-Loss Analysis of CMOS Full Adder Circuits |
| 193 |
2018 |
Design and Performance Analysis of 32 Bit VLSI Hybrid adder |
| 194 |
2018 |
Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders |
| 195 |
2018 |
SEDA - Single Exact Dual Approximate Adders for Approximate Processors |
| 196 |
2018 |
A Novel Framework for Procedural Construction of Parallel Prefix Adders |
| 197 |
2018 |
Design of Swing Dependent XOR-XNOR Gates based Hybrid Full Adder |
| 198 |
2018 |
Formal Probabilistic Analysis of Low Latency Approximate Adders |
| 199 |
2018 |
High Precision, High Performance FPGA Adders |
| 200 |
2018 |
Concurrent Error Detectable Carry Select Adder with Easy Testability |
| 201 |
2018 |
Design Methodology to Explore Hybrid Approximate Adders for EnergyEfficient Image and Video Processing Accelerators |
| 202 |
2018 |
Design Of 3 Bit Adder Using 6 Transistors In Mentor Graphics |
| 203 |
2018 |
A Theoretical Framework for Quality Estimation and Optimization of DSP Applications Using Low-Power Approximate Adders |
| 204 |
2018 |
Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures |
| 205 |
2018 |
Power-Efficient Approximate SAD Architecture with LOA Imprecise Adders |
| 206 |
2018 |
Efficient Modular Adder Designs Based on Thermometer and One-Hot Coding |
| 207 |
2018 |
Design of a Scalable Low-Power 1-bit Hybrid Full Adder for Fast Computation |
| 208 |
2018 |
Block-based Carry Speculative Approximate Adder for Energy-Efficient Applications |
| 209 |
2018 |
FPGA Based Performance Comparison of Different Basic Adder Topologies with Parallel Processing Adder |
| 210 |
2018 |
A novel design gate based low cost configurable R0 puf using reversible logic gates |
